Experience: 6+ years
Define and implement
comprehensive SoC verification strategies and plans
covering all functional and performance aspects.
Lead the development of
UVM/SystemVerilog-based verification environments
for complex SoC/IP subsystems.
Drive
end-to-end SoC verification
, including integration of IP-level environments into SoC-level testbenches.
Develop and maintain
test plans, test cases, and coverage models
(functional, code, and assertion coverage).
Create and debug
test scenarios, sequences, and scoreboards
to validate system functionality.
Work on
simulation, emulation, and formal verification tools
to ensure design correctness.
Analyze failures, debug root causes, and collaborate with design teams for timely resolution.
Drive
coverage closure and sign-off criteria
, ensuring high-quality deliverables.
Mentor junior engineers and provide technical leadership within the verification team.
Collaborate closely with cross-functional teams including
RTL design, architecture, firmware, and physical design
.
Preferred Skills
Experience with
low-power verification (UPF/CPF)
.
Knowledge of common SoC protocols (e.g.,
AXI, AHB, APB, PCIe, USB, Ethernet
).
Exposure to
emulation platforms
(Palladium, Veloce, ZeBu, etc.).
Familiarity with
formal verification methodologies
.
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