Drive the multi-year execution of the coherent interconnect roadmap, ensuring technical milestones align with System-on-a-chip (SoC) platform goals.
Work with SoC and Internet Protocols (IP) architects to co-define the microarchitecture of the coherent fabric, providing design-led insights on topology, routing, flow control, Quality of Service (QoS), and coherency protocols (e.g., Advanced Microcontroller Bus Architecture (AMBA) Coherent Hub Interface (CHI), AXI Coherency Extensions (ACE)).
Lead the end-to-end IP development process, translating architectural concepts into quality Register-Transfer Level (RTL) specifications and managing the integration of Physical Design (PD) and verification feedback.
Own the delivery of Power, Performance, and Area (PPA). Implement advanced design techniques to ensure the fabric provides an engaging advantage for Google’s silicon.
Minimum qualifications:
Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience.
15 years of experience with managing the implementation of IP blocks (e.g., Network-on-Chip (NoC) or memory subsystems) through multiple production tape-outs.
15 years of experience in Application-Specific Integrated Circuit (ASIC)/SoC design.
10 years of experience with computer architecture concepts, including microarchitecture, cache hierarchy, pipelining, and memory subsystems.
Preferred qualifications:
Master's degree or PhD in Electrical Engineering, Computer Engineering or Computer Science.
Experience in implementing snoop filters, distributed caches, and optimizing coherent traffic.
Ability to analyze performance requirements and drive PPA optimizations in NoC fabrics.
