Verify designs using verification techniques and methodologies.
Work cross-functionally to debug failures and verify the functional correctness of the design.
Provide test plans, including verification strategy, environment, components, stimulus, checks, and coverage; ensure documentation is easy to use.
Lead and manage verification activities for subsystems or SoCs.
Develop all aspects of logic verification infrastructure and methodology for mobile SoC IP or subsystem blocks.
Minimum qualifications:
Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, a related technical field, or equivalent practical experience.
10 years of experience with IP and subsystem verification, particularly with fabric IP and memory controllers.
10 years of experience developing UVM (Universal Verification Methodology) testbenches.
Experience developing verification components using SystemVerilog.
Preferred qualifications:
Master's degree or PhD in Electrical Engineering, Computer Engineering or Computer Science, with an emphasis on computer architecture.
Experience in low-power design verification.
Experience in formal verification.
