<p>EnCharge AI is a leader in advanced AI hardware and software systems for edge-to-cloud computing. EnCharge’s robust and scalable next-generation in-memory computing technology provides orders-of-magnitude higher compute efficiency and density compared to today’s best-in-class solutions. The high-performance architecture is coupled with seamless software integration and will enable the immense potential of AI to be accessible in power, energy, and space constrained applications. EnCharge AI launched in 2022 and is led by veteran technologists with backgrounds in semiconductor design and AI systems.</p>
<div class="elementToProof"><strong>Staff / Senior Staff Engineer: Static Timing Analysis (STA) Lead.</strong></div>
<div class="elementToProof">We are seeking a high-caliber<span class="Apple-converted-space"> </span><strong>Staff or Senior Staff Engineer</strong> to lead SOC Timing Convergence. This is a critical leadership role for a driven,<span class="Apple-converted-space"> </span><strong>"go-getter"</strong><span class="Apple-converted-space"> </span>engineer who excels at navigating the complexities of modern, large-scale SOC designs. You will be the bridge between Architecture, RTL, DFT, and Physical Design to ensure a predictable, high-performance path to tape-out.</div>
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<div class="elementToProof"><strong>The Role</strong></div>
<div class="elementToProof">As a lead for SOC Timing or SubChip Timing, you will own the strategy for convergence. You will identify bottlenecks early in the design cycle ("left-shifting") and drive cross-functional alignment to meet aggressive Power, Performance, and Area (PPA) targets.</div>
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<div class="elementToProof"><strong>Key Responsibilities</strong></div>
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<div class="elementToProof"><strong>Timing Convergence Leadership:</strong> Drive full-chip SOC timing closure across all corners and modes (func, shift, capture, etc.).</div>
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<div class="elementToProof"><strong>Cross-Functional Coordination:</strong> Partner with<span class="Apple-converted-space"> </span><strong>Architecture</strong> to validate timing feasibility,<span class="Apple-converted-space"> </span><strong>RTL</strong> to optimize logic structures, and<span class="Apple-converted-space"> </span><strong>DFT</strong> to streamline test-mode timing.</div>
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<div class="elementToProof"><strong>Left-Shift Strategy:</strong> Proactively identify and resolve structural timing issues, congestion, and high-latency paths early in the RTL/Synthesis phase to ensure predictable physical design execution.</div>
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<div class="elementToProof"><strong>Advanced Analysis:</strong> Perform complex timing tasks including<span class="Apple-converted-space"> </span><strong>CPPR/CRPR</strong> analysis,<span class="Apple-converted-space"> </span><strong>NoC</strong> (Network-on-Chip) timing, and constraint validation (SDC).</div>
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<div class="elementToProof"><strong>Automation & Agility:</strong> Architect and build sophisticated automation utilities (Tcl, Python, Perl) to accelerate timing sign-off, reduce manual audits, and improve schedule agility.</div>
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<div class="elementToProof"><strong>PPA Optimization:</strong> Drive best-in-class PPA by guiding physical design teams on floorplanning, clock tree synthesis (CTS) strategies, and placement optimizations.</div>
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<div class="elementToProof"><strong>Requirements & Qualifications</strong></div>
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<div class="elementToProof"><strong>Experience:</strong> 9 to 14 years of hands-on experience in STA and Timing Closure on advanced process nodes (7nm, 5nm, or below).</div>
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<div class="elementToProof"><strong>Critical Thinking:</strong> Proven ability to debug complex timing violations, identify root causes (e.g., data-to-clock skew, crosstalk), and propose architectural or physical solutions.</div>
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<div class="elementToProof"><strong>Technical Mastery:</strong> * Expertise in industry-standard sign-off tools (e.g., PrimeTime, Tempus). Preferable Tempus tool.</div>
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<div class="elementToProof">Deep understanding of<span class="Apple-converted-space"> </span><strong>Multi-Mode Multi-Corner (MMMC)</strong> challenges and Hierarchical vs. Flat timing closure.</div>
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<div class="elementToProof">Proficiency in SDC/CDC constraints.</div>
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<div class="elementToProof"><strong>Soft Skills:</strong> Strong leadership presence with the ability to influence cross-functional teams and drive execution in a fast-paced environment.</div>
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<div class="elementToProof"><strong>Education:</strong> B.Tech/M.Tech<span class="Apple-converted-space"> </span>in Electrical/Electronics Engineering or a related field.</div>
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<div class="elementToProof"><strong>Why Join Us?</strong></div>
<div class="elementToProof">You will have the autonomy to define the timing methodology for next-generation silicon. This role offers the opportunity to tackle the industry's toughest frequency and power challenges while building the automation infrastructure that defines our engineering excellence.</div>
