We are looking for a motivated and talented Design Verification Engineer to join our team in creating next-generation Power management solutions.
Job Responsibilities
Define and own verification plans, methodologies, and coverage strategies for complex SoC designs
Architect and implement verification environments from scratch and enhance existing frameworks
Drive block-level, subsystem-level, and full-chip verification
Build Agents, sequences, drivers, monitors, and scoreboards as part of automation.
Integrate industry-standard VIPs, create custom transactor.
Lead end2end verification, including: Gate level simulations and debugs, coverage analysis and closure, regression, triage failures, and ensure quality sign-off
Mentor junior and mid-level verification engineers
Act as technical lead or owner for key verification deliverables
Bachelor's degree in Electrical Engineering or equivalent practical experience.
Overall 7-8+ years of experience and 2 years of experience with verification methodology such as universal verification methodology (UVM).
Experience with industry-standard simulators, revision control systems, and regression systems.
Experience with Architecting block the full verification lifecycle.
Excellent problem solving and communication skills.
Construct testbenches components like scoreboard, agents, sequencers, and monitors
Debugging RTL and Gate simulations and working with cross functionals team to verify fixes
Converting verification tests to test patterns and assisting Test Engineers on ATE vector bring up
Experience developing and maintaining verification testbenches, test cases, and test environments.
Understanding of SoC architecture and functionality, Mixed signal designs.
Good knowledge of analog components : ADC, DAC, PLL, Oscilators and PI controllers.
Passion for learning and engineering great solutions
Proven written and verbal communication skills that demonstrate clarity of thought and conviction
Working knowledge of one or more scripting languages (Perl, Python) and ability to use them to automate/accelerate verification and analysis tasks
Experience of directed and constrained random verification methodology Good knowledge in UVM, Verilog, SV, C/C++, Shell, Python
Strong debug, logical thinking and analytical skills
Renesas is an embedded semiconductor solution provider driven by its Purpose ‘
To Make Our Lives Easier
.’ As the industry’s leading expert in embedded processing with unmatched quality and system-level know-how, we have evolved to provide scalable and comprehensive semiconductor solutions for automotive, industrial, infrastructure, and IoT industries based on the broadest product portfolio, including High Performance Computing, Embedded Processing, Analog & Connectivity, and Power.
With a diverse team of over 21,000 professionals in more than 30 countries, we continue to expand our boundaries to offer enhanced user experiences through digitalization and usher into a new era of innovation. We design and develop sustainable, power-efficient solutions today that help people and communities thrive tomorrow, ‘
To Make Our Lives Easier
.’
At Renesas, you can:
Launch and advance your career
in technical and business roles across four Product Groups and various corporate functions. You will have the opportunities to explore our hardware and software capabilities and try new things.
Make a real impact
by developing innovative products and solutions to meet our global customers' evolving needs and help make people’s lives easier, safe and secure.
Maximize your performance and wellbeing
in our flexible and inclusive work environment. Our people-first culture and global support system, including the remote work option and Employee Resource Groups, will help you excel from the first day.
Are you ready to own your success and make your mark?
Join Renesas. Let’s
Shape the Future
together.
Renesas Electronics is an equal opportunity and affirmative action employer, committed to supporting diversity and fostering a work environment free of discrimination on the basis of sex, race, religion, national origin, gender, gender identity, gender expression, age, sexual orientation, military status, veteran status, or any other basis protected by law. For more information, please read our
Diversity & Inclusion Statement
.