Job Description-STA
We are looking for an Experienced STA Leader. This is a unique opportunity for bringing timing & convergence for SOC, driving the design changes, while being responsible for end2end timing closure and timing signoff. It includes the ownership for driving timing signoff criteria, design clocking, constraints development and validation. Expected Interface with critical domains like IP, Functional Integration, DFT & Verification while working closely with Physical implementation team for providing feedback, timing convergence and ECO creation, timing/noise model build, GLS support and final timing signoff.
Responsibilities
Ability to understand advanced digital design architectures and clocking structures to help manage Functional/Scan/MBIST timing constraints with multiple clocks.
Expertise in SOC IO constraints developments.
May have to own bottom-up partition-level integration and top-down design partitions constraints.
Expertise in Advance Timing Analysis, Debug and timing convergence, ECO creation with signal integrity & EM/IR.
Knowledge about SDF, GLS, and able to debug timing failures.
Hands-on experience of working on technology nodes like 28nm, 16nm, 10nm, 7nm.
Good knowledge of EDA tools from RC, DC, PT, PTSI.
Good knowledge of Synthesis, Floor planning, place & route, power and clock distribution, pin placement and timing analysis.
Contribution in flow/methodology related scripting as part of design implementation.
More information about NXP in India...
#LI-2734
