Work as part of the EdgeTPU compiler team, including analyzing and improving the compiler quality and performance on optimization decisions, correctness and compilation time.
Develop parallelization and scheduling algorithms to optimize compute and data movement costs to execute ML workloads on the EdgeTPU.
Work on efficient mapping of AI models and other key workloads into EdgeTPU instructions through the compiler.
Manage a team of experienced compiler engineers.
Collaborate with Machine Learning (ML) model developers, researchers, and EdgeTPU hardware/software teams to accelerate the transition from research ideas to exceptional user experiences running on the EdgeTPU.
Minimum qualifications:
Bachelor's degree in Computer Science, Electrical Engineering, a related technical field, or equivalent practical experience.
8 years of experience in compiler development, including machine learning optimization and experience with ML accelerators (e.g., Tensor Processing Units (TPUs) or Graphics Processing Units (GPUs))
8 years of experience with embedded operating systems and experience with compilers (e.g., optimization, parallelization, etc.)
2 years of experience in a people management or team leadership role.
Experience in Multi-Level Intermediate Representation (MLIR) or Low Level Virtual Machines (LLVM).
Preferred qualifications:
Master's degree or PhD in Computer Science or related technical field.
3 years of experience working in a complex, matrixed organization.
Experience compiling for heterogeneous architectures across IPs, including but not limited to CPU, GPU, and NPUs.
Compiler development experience in the context of accelerator-based architectures, vector instruction optimizations, or vectorizing compilers.
