At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology.
Software Architect – Virtual & Hybrid Platform Integration and Software Bring-up
Role Overview
We are looking for a
seasoned Software Architect
to join the team, responsible for
Virtual and Hybrid platform integration
and
pre‑silicon software bring-up
. The candidate will work on complex emulator- and FPGA-based platforms to enable early software development and validation for mobile, hyperscale, and automotive SoCs.
This is a
hands-on individual contributor role
requiring deep technical expertise, strong cross‑functional collaboration, and the ability to independently drive complex technical deliverables from architecture to execution.
Key Responsibilities
Architect, integrate, and debug
Virtual and Hybrid platforms
combining RTL, transactors, and virtual models for pre‑silicon enablement.
Develop systemC and Multithreaded C++ models and Transactors necessary for bringup of software on a Hybrid platform.
Lead
software bring-up
on pre‑silicon platforms (emulators / FPGA prototypes), including:
Bare‑metal environments
Linux OS
Android
Windows (where applicable)
Drive end‑to‑end platform readiness from early boot (ROM, bootloaders) to OS stability.
Work closely with
RTL, IP, firmware, validation, and customer teams
to define requirements, align interfaces, and plan deliverables.
Debug complex software and platform issues using:
Waveform analysis
Software debuggers (GDB, JTAG-based, emulator debuggers, etc.)
Logs and traces
Identify root causes across HW/SW boundaries and propose robust architectural fixes.
Technical Expertise & Qualifications
Required Skills
Strong background in
software architecture
with proven experience building and debugging
complex pre‑silicon platforms
.
Hands‑on experience integrating
RTL with virtual and hybrid environments
.
Deep understanding of
SoC architecture
and system-level behavior across:
Mobile
Hyperscaler / Datacenter
Automotive platforms
Expert knowledge of
AMBA protocols and interconnects
.
Proven experience working with and integrating key SoC IPs such as:
UFS, NVMe, PCIe
Strong proficiency in
software debugging methodologies
, including waveform-based debug and HW/SW co-debug.
Solid programming and scripting skills (C/C++, Python, shell scripting preferred).
Hands on experience on Multi-Threaded aspects, its challenges and tools to manage deadlocks
Preferred / Value-Add Skills
Experience with
SystemC modeling
and transaction-level modeling; ability to modify or develop models is a strong plus.
Prior experience working with
emulators and FPGA-based platforms
(Palladium, Protium, or similar).
Familiarity with
GenAI / LLM-based workflows
applied to EDA, debugging, automation, or productivity acceleration.
Knowledge of platform performance analysis and optimization.
Collaboration & Leadership Expectations
Strong ability to work across
cross‑functional teams
and with external customers to:
Understand complex, multi-team requirements
Translate them into executable technical plans
Ability to
independently lead and execute projects
, owning outcomes end to end.
While this is an
individual contributor role
, prior experience in:
Mentoring junior engineers
Technical leadership
Team or project ownership
is highly valued.
Candidate Profile
A
senior, hands-on technologist
with strong problem-solving skills and a system-level mindset.
Comfortable operating in ambiguous, fast‑moving environments.
Motivated to align with
long‑term technical growth
and strategic platform evolution within Cadence.
We’re doing work that matters. Help us solve what others can’t.
