Verify designs using verification techniques and methodologies.
Work cross-functionally to debug failures and verify the functional correctness of the design.
Provide test plans, including verification strategy, environment, components, stimulus, checks, and coverage, and ensure documentation is easy to use.
Develop and execute performance verification plans for compute clusters and analyze architectural bottlenecks of Google's Tensor System on a chip (SoC).
Analyze pipeline stalls, branch mispredictions, and memory subsystem bottlenecks to identify deviations from the performance model and architecture projections.
Minimum qualifications:
Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience.
4 years of experience in SoC design/verification.
Preferred qualifications:
Master's degree or PhD in Electrical Engineering, Computer Engineering or Computer Science, with an emphasis on computer architecture.
Experience in low-power design verification.
Knowledge of performance and latency architecture for an ARM based SoC.
