Participate in the design, implementation and integration of Chassis, subsystems and SoC.
Perform RTL coding, function/performance simulation debug, and Lint/Clock-Domain Crossing (CDC)/Formal Verification(FV)/Unified Power Format (UPF) checks.
Participate in design debug, and code review in coordination with other IPs Design Verification (DV) teams and physical design teams.
Coordinate with various IP teams to meet schedule and quality requirements.
Communicate and work with multi-disciplined and multi-site teams.
Minimum qualifications:
Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience.
8 years of experience with digital logic design principles, RTL design concepts, and languages, such as Verilog or SystemVerilog.
Experience with logic synthesis techniques to optimize RTL code, performance and power, as well as low-power design techniques.
Experience in SoC designs and integration flows.
Preferred qualifications:
Master's degree or PhD in Electrical Engineering, Computer Engineering or Computer Science.
Experience with a scripting language like Perl or Python.
Knowledge of arithmetic units, bus architectures, processor design, accelerators, or memory hierarchies.
