Build, manage and lead the team responsible for post silicon validation of Artificial Intelligence/Machine Learning (AI/ML) System on a Chip (SoCs).
Lead and enable the team to power-on Tensor Processing Unit (TPU) SoC silicon and bring it up through reset, boot and bare metal content or Operating System (OS).
Drive the enablement of all key high-speed serial and parallel interfaces in TPU silicon.
Collaborate with architecture, design and verification teams to propose, implement and enable DFV (Design for Validation) and DFD (Design for Debug) features on silicon and develop and review post silicon test plans, coverage and debug.
Drive all the people management functions including, but not limited to, hiring, people development, prioritizing and managing resources to achieve project execution timelines.
Minimum qualifications:
Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience.
8 years of experience in bringing-up and validating at least one high-speed serial or parallel interface (e.g., PCIe, UCIe, DDR, HBM, Ethernet, etc.).
8 years of experience in analyzing board schematics and working with scopes, logic analyzers, protocol analyzers, BERT, etc
3 years of experience leading a post-silicon validation team with ownership on electrical validation of one or more high speed interfaces.
Experience of co-working with firmware/software teams to debug issues.
Experience in people management, developing employees.
Preferred qualifications:
Experience in bringing up multiple serial and parallel high speed interfaces.
Experience in programming/scripting in C, C++, Python, Perl or TCL.
Experience in using emulation or prototyping platforms.
Experience in end-to-end post-silicon validation of an SoC (bring-up, features validation, electrical, power and performance characterization, etc.).
Understanding of SoC architecture and interfaces (e.g., AXI, DDR, PCIe, etc.).
