Define and architect SoC-level debug and trace features, heavily utilizing ARM CoreSight and custom debug IPs to enable deep visibility into complex, multi-die AI systems.
Partner with IP design, SoC integration, Design Verification (DV), and low-level software/firmware teams to translate architectural requirements into executable specifications.
Drive the definition of the SoC power management architecture, including power domains, low-power states, and power sequencing.
Conduct PPA (Power, Performance, Area) analysis to make data-driven architectural decisions.
Architect robust and scalable boot, initialization, and reset sequences across the entire SoC and Security. Define hardware security architectures, including secure boot, cryptographic isolation, and debug security/entitlement mechanisms.
Minimum qualifications:
Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, a related field, or equivalent practical experience.
8 years of experience in ASIC/SoC architecture, logic design, or systems engineering.
Experience defining and specifying boot, reset, and power management architectures for SoCs.
Experience in hardware security principles (e.g., secure boot, hardware root of trust, secure debug).
Experience in debug and trace architectures, specifically with ARM CoreSight infrastructure.
Preferred qualifications:
Master’s degree or PhD in Electrical Engineering, Computer Engineering, or a related field.
Experience with AI/ML accelerator architectures or high-performance computing (HPC) SoCs.
Experience taking a complex SoC from early concept definition through to post-silicon bring-up and debug.
Knowledge of PCIe (Peripheral Component Interconnect Express) architecture and integration.
Excellent communication and documentation skills, with the ability to lead and influence cross-functional engineering teams.
