Manage the physical design of the System on Chips (SoCs) to tape-out while collaborating with multiple team members.
Evaluate and develop physical design methodologies and determine the System on Chip (SoC) flow.
Work with architects and logic designers to drive architectural feasibility studies, develop timing, power, and area design goals, and explore Register Transfer Level (RTL)/design tradeoffs for physical design closure.
Participate in design reviews and track issue resolution, and engage in technical and schedule tradeoff discussions. Create execution plans for projects and manage team efforts from concept to working silicon in volume.
Understand architecture and design specifications with the team, and define physical design strategies to meet quality and schedule goals.
Minimum qualifications:
Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience.
10 years of technical experience in silicon implementation and chip integration.
8 years of management experience in ASIC development teams.
Experience in engineering across physical design, implementation, and Graphic Data System (GDS) tape-out.
Experience in floorplanning, block integration, static timing analysis, sign-off.
Preferred qualifications:
Experience in leading physical design teams working on digital designs that have taped-out and produced working silicon and delivering silicon.
Knowledge of delivery of silicon in technology process nodes.
Understanding of circuit design, device physics and submicron technology.
Ability to lead cross-functional teams.
