Contribute to DFT strategy and architecture (e.g., hierarchical DFT, Memory Built-In Self Test (MBIST), ATPG).
Develop and drive DFT validation strategy for the SoC and Insert DFT logic, boundary scan, scan chains, DFT Compression, Logic BIST, TAP controller, Clock Control block, and other DFT IP blocks.
Integrate and connect MBIST logic including test collar around memories, MBIST controllers, eFuse logic, and connect to core and TAP interfaces.
Document DFT architecture, test sequences, and boot-up sequences associated with test pins.
Execute Post Silicon ATE Bring up and sustenance and Lead complete DFT phase at wafer Level.
Minimum qualifications:
Bachelor's degree in Electrical Engineering, a related field, or equivalent practical experience.
8 years of experience in DFT domain.
8 years of experience using electronic design automation (EDA) test tools (e.g., Spyglass, Tessent, Synopsys).
Experience with ASIC DFT synthesis, STA, simulation, and verification flow.
Experience working with ATE engineers (e.g., silicon bring-up, patterns generation, debug, validation on automatic test equipment, and debug of silicon issues, etc.).
Preferred qualifications:
Experience leading the DFT implementations.
Experience in managing or mentoring the team technically.
Experience with advanced technology nodes (5nm/3nm), 2.5D/3D-IC packaging, or high-speed I/O (SerDes/DDR) testing methodologies.
Experience managing global technical teams and driving vendor engagement.
Ability to drive cross-functional timing closure, power analysis, and IR-drop mitigation for high-frequency designs.
