Manage Register-Transfer Level (RTL) design, Design Verification (DV) and physical design of System-on-Chip (SoC) to tape-out while working with multiple team members.
Evaluate and develop SoC design and Integration methodologies and decide on the SoC flow.
Work with architects and reasoning designers to drive architectural feasibility studies, develop timing, power and area design goals, and explore RTL/design trade-offs for physical design closure.
Participate in design reviews and track issue resolution, and engage in technical and schedule trade-off discussions. Create execution plans for projects and manage team efforts from concept to working silicon in volume.
Understand architecture and design specifications with the larger team, and define physical design strategies and tactics to meet quality and schedule goals.
Minimum qualifications:
Bachelor's degree in Electrical Engineering, a related field, or equivalent practical experience.
10 years of experience with silicon design, DV, implementation and chip integration.
Experience with management in Application-Specific Integrated Circuit (ASIC) development teams.
Experience in leading design teams with working on digital designs that have taped-out and produced working silicon and delivering silicon.
Preferred qualifications:
Experience with extraction of design parameters, Quality of Results (QoR) metrics, and analyzing data trends.
Experience with engineering across design, DV, physical design, implementation, Graphic Data System (GDS) tape-out.
Knowledge of delivery of silicon in technology process nodes.
Ability to lead cross-functional teams.
