Own microarchitecture and implementation of complex IPs and subsystems.
Take ownership of RTL implementation and quality checks of one or more modules.
Contribute to design methodology, libraries, debug, code review in coordination with other IPs Design Verification (DV) teams and physical design teams.
Identify and drive Power, Performance and Area (PPA) improvements for the modules owned.
Participate in synthesis, timing/power closure, and FPGA/silicon bring-up.
Minimum qualifications:
Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience.
8 years of experience in Application-Specific Integrated Circuit/System on a chip (ASIC/SoC) development with Verilog/SystemVerilog.
Experience in micro-architecture and design of IPs and Subsystems.
Experience in ASIC design verification, synthesis, timing/power analysis, and Design for Testing (DFT).
Preferred qualifications:
Experience with programming languages (e.g., Python, C/C++ or Perl).
Experience in SoC designs and integration flows.
Knowledge of arithmetic units, processor design, accelerators, bus architectures, fabrics/NoC or memory hierarchies.
Knowledge of high performance and low power design techniques.
