Define and drive to the implementation of physical design methodologies.
Take ownership of one or more physical design partitions.
Drive to the closure of timing and power consumption of the design.
Contribute to design methodology, libraries, and code review.
Define the physical design related rule sets for the functional design engineers.
Minimum qualifications:
Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience.
4 years of experience with advanced design, including clock/voltage domain crossing, Design for Testing (DFT), and low power designs.
Experience with System on a Chip (SoC) cycles.
Experience with performance, frequency, and low-power designs.
Preferred qualifications:
Master's Degree in Electrical Engineering or a related field.
Experience coding with System Verilog and scripting with TCL.
Experience with VLSI design in SoC.
Experience with multiple cycles of SoC in ASIC design.
Experience with layout verification and design rules.
