Drive development of complex IPs and subsystems along with a team of engineers.
Own micro-architecture and implementation of IPs and subsystems.
Work with architecture, firmware and software teams to drive feature closure and develop micro-architecture specifications.
Drive design methodology, libraries, debug, code review in coordination with other IPs Design Verification (DV) teams and physical design teams.
Identify and drive power, performance and area improvements for the domains owned.
Minimum qualifications:
Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience.
10 years of experience in ASIC development with Verilog/SystemVerilog, Vhsic Hardware Description Language (VHDL).
Experience in micro-architecture and design IPs and Subsystems.
Experience in ASIC design verification, synthesis, timing/power analysis, and Design for Testing (DFT).
Preferred qualifications:
Experience with scripting languages (e.g., Python or Perl).
Experience in SoC designs and integration flows.
Knowledge of bus architectures, fabrics/NoC, processor design, accelerators, or memory hierarchies..
Knowledge of high performance and low power design techniques.
