Build full chip emulation or FPGA prototypes from complex SoC designs and deliver to multiple customers such as Software, Firmware, Platform, and Post-Silicon Validation teams.
Influence the Design and Verification teams to add emulation friendly model development.
Bring up of system level emulation models through reset, boot, and bare metal content or OS.
Work with Architects, Designers, Software Engineers, Pre and Post-Silicon Verification Engineers to develop test plans, coverage, and to reproduce failures on emulation.
Develop, execute, and debug full-chip/System on a Chip (SoC) tests on emulation platforms. Explore new verification and emulation methodologies and implement them.
Minimum qualifications:
Bachelor's degree or equivalent practical experience.
5 years of experience with full-chip/SoC verification (e.g., test definition, creation, execution, and debug).
Experience developing full-chip/SoC tests using the environments/tools (e.g., ASM, C, C++, Perspec, OS, or drivers).
Experience with industry standard emulator technologies (e.g., HAPS, Zebu, Veloce, or Palladium) ranging from build tools to advanced capabilities (e.g. power aware emulation).
Experience with execution and RTL/firmware/software debug on hardware emulation (e.g., ZeBu Server, Palladium, Veloce) or FPGA (e.g., Xilinx, Altera).
Preferred qualifications:
Experience with EDA debug tools (e.g., Verdi, SimVision/Indago, GDB).
Experience in programming and scripting in C, C++, Python, Perl, or TCL.
Experience with AI usage for enhancing emulation flows and debug.
Understanding of SoC architecture and interfaces (e.g., DDR, PCIe, etc.).
Understanding of RTL to Emulation/FPGA flows including emulation test benches, DFT and virtual machines (e.g., transactors/accelerated VIPs, hybrid, in-circuit emulation).
