Complete all Test Design Rule Checks (TDRC) and design changes to fix TDRC violations to achieve high test quality and support the post-silicon test team.
Generate, simulate, and optimize high-quality manufacturing test patterns (Stuck-at, Transition, Path Delay, and IDDQ) for Automated Test Equipment (ATE), while actively managing pattern volume and test time reduction (TTR) strategies.
Develop and verify specialized test sequences and parametric measurement patterns to validate and characterize Analog IPs (PLLs, LDOs, ADCs) and high-speed I/Os (SerDes, DDR, PCIe, MIPI).
Partner closely with the Product Engineering teams to validate patterns on silicon, lead the diagnosis of ATE failures, and perform root-cause analysis to support yield learning and rapid ramp-to-production.
Enhance DFT flows and methodologies using scripting (Tcl, Perl, Python) to automate insertion and validation processes, ensuring a "correct-by-construction" approach for future SoC.
Minimum qualifications:
Bachelor's degree in Electrical Engineering or a related field, or equivalent practical experience.
3 years of experience in DFT specification definition architecture and insertion.
Experience with Application-Specific Integrated Circuit (ASIC) DFT synthesis, Static Timing Analysis (STA), simulation, and verification flow.
Experience in silicon bring-up, debug, and validation of DFT features on ATE, debugging Automatic Test Pattern Generation (ATPG) patterns, Compressed ATPG patterns, Memory Built-In Self-Test (MBIST) and Joint Test Action Group (JTAG) related issues.
Experience with Scan insertion, ATPG, Gate Level Simulations and Silicon Debug, Low Power designs, BIST, JTAG, IJTAG tools and flow.
Preferred qualifications:
Master's degree or PhD in Electrical Engineering, Computer Engineering or Computer Science or a related field.
Experience with silicon bring-up, ATE pattern debug, and failure analysis (diagnosis) to support yield improvement.
Experience in multi-voltage, and multi-clock domain SoCs.
Familiarity with generating and validating patterns for High-Speed I/Os (HSIO) and Analog/Mixed-Signal IPs.
Proficiency with a scripting language like Perl, Tcl or Python.
