Develop and execute verification plans. Architect, develop and maintain verification test benches that support both random and directed testing.
Participate in design, architecture and code reviews. Work with micro architects, architects and design teams and influence design decisions/feature intercepts.
Lead performance validation for both pre-silicon and post-silicon. Work with emulation/FPGA prototyping teams in verifying system level use cases. Drive convergence of verification and coverage plans towards high quality and on-time tape-out. Drive methodology initiatives to improve efficiency and design quality.
Lead or Manage a team of design verification engineers focusing on IP, Subsystem/SoC verification at unit, cluster, subsystem and full chip levels.
Influence architectural feature level decisions with the understanding of workload performance. Adopt methodology improvements using AI and EDA capability to drive efficiency gains and innovation.
Minimum qualifications:
Bachelor's degree in Electrical Engineering or equivalent practical experience.
10 years of experience in the verification of IP designs such as IP, SoC, vector CPUs, etc.
8 years of experience with verification methodology such as Universal Verification Methodology (UVM).
4 years of experience in people management, developing employees.
Experience with SystemVerilog, SystemVerilog Assertions (SVA) and functional coverage.
Preferred qualifications:
Master's degree in Electrical Engineering or a related field.
Experience verifying digital systems using standard IP components or interconnects (e.g., microprocessor cores, hierarchical memory subsystems).
Experience creating and using verification components and environments in standard verification methodology.
Experience with ASIC standard interfaces and memory system architecture.
Experience in verification of AI/ML Accelerators.
