Debug tests with design engineers to deliver functionally correct design blocks.
Perform integration checks like connectivity.
Write tests in SystemVerilog (SV) and assembly/C.
Perform SoC Boot, configuration and data path verification at SoC level.
Participate in design debug, code review in coordination with other IPs Design Verification (DV) teams, Silicon validation teams.
Minimum qualifications:
Bachelor's degree in Electrical Engineering or equivalent practical experience.
4 years of experience with verification methodology such as universal verification methodology (UVM).
2 years of experience in the verification of intellectual property (IP) designs such as IP, system on a chip (SoC), vector CPUs, etc.
Experience with verification methodologies and languages such as UVM or SystemVerilog.
Experience developing and maintaining verification testbenches, test cases, and test environments.
Preferred qualifications:
Master's degree in Electrical Engineering or a related field.
Experience with industry-standard simulators, revision control systems, and regression systems.
Experience with the full verification lifecycle.
Experience in artificial intelligence/machine learning (AI/ML) accelerators or vector processing units.
Excellent problem solving and communication skills.
