Verify designs using verification techniques and methodologies.
Work cross-functionally to debug failures and verify the functional correctness of the design.
Provide test plans, including verification strategy, environment, components, stimulus, checks, and coverage, and ensure documentation is easy to use.
Minimum qualifications:
Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, a related field, or equivalent practical experience.
1 year of experience with Universal Verification Methodology (UVM), System Verilog and test planning.
Preferred qualifications:
Master's degree or PhD in Electrical Engineering, Computer Engineering or Computer Science, with an emphasis on computer architecture.
Experience in low-power design verification.
Experience developing and maintaining verification test benches, test cases, and test environments.
