Revolutionize Machine Learning (ML) workload characterization and benchmarking, and propose capabilities and optimizations for next-generation TPUs.
Develop architecture specifications that meet current and future computing requirements for AI/ML roadmap. Develop architectural and microarchitectural power/performance models, microarchitecture and RTL designs and evaluate quantitative and qualitative performance and power analysis.
Partner with hardware design, software, compiler, Machine Learning (ML) model and research teams for effective hardware/software codesign, creating high performance hardware/software interfaces.
Develop and adopt advanced AI/ML capabilities, drive accelerated and efficient design verification strategies and implementations.
Use AI techniques for faster and optimal Physical Design Convergence -Timing, floor planning, power grid and clock tree design etc. Investigate, validate, and optimize DFT, post-silicon test, and debug strategies, contributing to the advancement of silicon bring-up and qualification processes.
Minimum qualifications:
PhD degree in Electronics and Communication Engineering, Electrical Engineering, Computer Engineering or related technical field, or equivalent practical experience.
Experience with accelerator architectures and data center workloads.
Experience in programming languages (e.g., C++, Python, Verilog), Synopsys, Cadence tools.
Preferred qualifications:
2 years of experience post PhD.
Experience with performance modeling tools.
Knowledge of arithmetic units, bus architectures, accelerators, or memory hierarchies.
Knowledge of high performance and low power design techniques.
