Document DFT architecture and test sequences, including boot-up sequence associated with test pins.
Participate in DFT logic insertion like scan and BIST at RTL and netlist level.
Perform DFT checks for scan coverage and memory Built-In Self Test (BIST).
Plan SoC/IP/Subsystems (SS) DFT and collaborate with cross-functional teams, DFT constraints development for timing closure and Physical Design (PD)/Static Timing Analysis (STA) support.
Perform quality check flows like Lint, CDC, of the DFT RTL in DFT modes. Participate in design debug, code review in coordination with other IPs Design Verification (DV) teams and Physical Design teams.
Minimum qualifications:
Bachelor's degree in Electrical Engineering, a related field, or equivalent practical experience.
3 years of experience in DFT specification and definition architecture and insertion.
2 years of experience with analog or mixed-signal IC design.
Experience with DFT (Design for Test) technologies such as Scan, ATPG (Algorithmic Test Pattern Generation) and MBIST (Memory Built in Self Test.
Experience with ASIC DFT synthesis, STA, simulation, and verification flow.
Preferred qualifications:
Master's degree in Electrical Engineering, or a related field.
Experience working with ATE engineers (e.g., silicon bring-up, patterns generation, debug, validation on automatic test equipment, and debug of silicon issues, etc.).
Experience in SoC cycles, including silicon bring-up and silicon debug activities.
Experience in IP integration (e.g., memories, test controllers, TAP, and MBIST).
Experience in fault modeling.
