Senior/Staff STA (Static Timing Analysis) Engineer
The STA Engineer is responsible for ensuring robust timing closure and signoff readiness for block- and full-chip designs across all modes and corners. This role owns timing constraint development and validation, performs detailed setup/hold and variation-aware analysis, and partners closely with Synthesis, CTS, Physical Design, and Design teams to debug violations and drive ECO-based optimizations through tapeout.
What you’ll do
Perform full-chip and block-level Static Timing Analysis (STA) across all modes and corners.
Analyze and debug setup, hold, recovery, removal, clock gating, and signal integrity-related timing violations.
Work closely with Physical Design, Synthesis, CTS, and Design teams to achieve timing closure.
Develop and maintain timing constraints including SDC creation, validation, and signoff readiness.
Drive timing closure through ECO implementation and timing optimization.
Analyze timing impact due to process, voltage, and temperature variations.
Support timing signoff for pre-layout and post-layout stages.
Perform cross-functional reviews for timing convergence and provide recommendations.
Generate timing reports and communicate closure status to project stakeholders.
What we’re looking for
4–12 years of experience in Static Timing Analysis (STA) and timing closure for block and/or full-chip designs.
Strong understanding of CMOS fundamentals, timing concepts, and semiconductor design flow.
Hands-on experience in setup/hold analysis, path-based analysis, OCV/AOCV/POCV, derates, and MMMC concepts.
Good understanding of clock tree, clock uncertainty, latency, skew, and jitter.
Experience in timing constraints development and debugging.
Strong knowledge of SDC, timing exceptions, false paths, multicycle paths, and case analysis.
Familiarity with timing closure techniques and ECO methodologies.
Hands-on experience with industry-standard STA tools such as Synopsys PrimeTime or Cadence Tempus.
Good scripting skills in Tcl, Perl, or Python.
Ability to analyze and resolve timing violations independently.
Nice to have
Exposure to low-power timing analysis and UPF/CPF-aware STA.
Familiarity with SI-aware timing, Crosstalk analysis, and IR-drop-aware timing closure.
Knowledge of advanced technology nodes and variation-aware signoff methodologies.
Exposure to automation and flow development.
Experience in cross-functional collaboration with PD, RTL, and Signoff teams.
Renesas is an embedded semiconductor solution provider driven by its Purpose ‘
To Make Our Lives Easier
.’ As the industry’s leading expert in embedded processing with unmatched quality and system-level know-how, we have evolved to provide scalable and comprehensive semiconductor solutions for automotive, industrial, infrastructure, and IoT industries based on the broadest product portfolio, including High Performance Computing, Embedded Processing, Analog & Connectivity, and Power.
With a diverse team of over 21,000 professionals in more than 30 countries, we continue to expand our boundaries to offer enhanced user experiences through digitalization and usher into a new era of innovation. We design and develop sustainable, power-efficient solutions today that help people and communities thrive tomorrow, ‘
To Make Our Lives Easier
.’
At Renesas, you can:
Launch and advance your career
in technical and business roles across four Product Groups and various corporate functions. You will have the opportunities to explore our hardware and software capabilities and try new things.
Make a real impact
by developing innovative products and solutions to meet our global customers' evolving needs and help make people’s lives easier, safe and secure.
Maximize your performance and wellbeing
in our flexible and inclusive work environment. Our people-first culture and global support system, including the remote work option and Employee Resource Groups, will help you excel from the first day.
Are you ready to own your success and make your mark?
Join Renesas. Let’s
Shape the Future
together.
Renesas Electronics is an equal opportunity and affirmative action employer, committed to supporting diversity and fostering a work environment free of discrimination on the basis of sex, race, religion, national origin, gender, gender identity, gender expression, age, sexual orientation, military status, veteran status, or any other basis protected by law. For more information, please read our
Diversity & Inclusion Statement
.
We have adopted a hybrid model that gives employees the ability to work remotely two days a week while ensuring that we come together as a team in the office the rest of the time. The designated in-office days are Tuesday through Thursday for innovation, collaboration and continuous learning.
