<p> </p>
<p data-start="220" data-end="237"><strong data-start="220" data-end="237">Role Overview</strong></p>
<p data-start="239" data-end="606">We are seeking a <strong data-start="256" data-end="285">Senior Staff DFT Engineer</strong> to join a rapidly growing <strong data-start="312" data-end="331">DFT design team</strong> focused on next-generation <strong data-start="359" data-end="382">AI accelerator SoCs</strong>. In this role, you will define, architect, and implement <strong data-start="440" data-end="480">current and future DFT/DFX solutions</strong>, supporting advanced SoC designs that leverage <strong data-start="528" data-end="605">innovative memory-centric compute and heterogeneous chiplet architectures</strong>.</p>
<p data-start="608" data-end="825">This is a highly hands-on role requiring both <strong data-start="654" data-end="706">deep technical execution and high-level planning</strong>, working across design, verification, product, and test teams to ensure robust manufacturability and silicon bring-up.</p>
<p data-start="608" data-end="825"> </p>
<p><strong>Location:</strong></p>
<p>Hybrid, working onsite at our Bengaluru, Karnataka, headquarters 3-5 days per week.</p>
<p data-start="608" data-end="825"> </p>
<hr data-start="827" data-end="830">
<h2 data-start="832" data-end="855">Key Responsibilities</h2>
<ul data-start="857" data-end="2040">
<li data-start="857" data-end="954">
<p data-start="859" data-end="954">Drive <strong data-start="865" data-end="896">DFT partitioning strategies</strong> for ATPG, including hierarchical and scalable approaches.</p>
</li>
<li data-start="955" data-end="1076">
<p data-start="957" data-end="1076">Implement <strong data-start="967" data-end="1005">ATPG compression and serialization</strong>, and perform <strong data-start="1019" data-end="1041">RTL scan insertion</strong> with associated design rule fixes.</p>
</li>
<li data-start="1077" data-end="1231">
<p data-start="1079" data-end="1231">Own <strong data-start="1083" data-end="1106">Memory BIST (MBIST)</strong> solutions, including <strong data-start="1128" data-end="1170">memory repair and in-system test (IST)</strong>, from implementation through verification and silicon debug.</p>
</li>
<li data-start="1232" data-end="1344">
<p data-start="1234" data-end="1344">Support <strong data-start="1242" data-end="1259">boundary scan</strong> and define <strong data-start="1271" data-end="1295">DFT mode constraints</strong> for IPs, providing timing feedback to STA teams.</p>
</li>
<li data-start="1345" data-end="1467">
<p data-start="1347" data-end="1467">Generate and integrate <strong data-start="1370" data-end="1381">DFT RTL</strong>, ensuring quality through RTL-level checks (e.g., linting and DFT rule verification).</p>
</li>
<li data-start="1468" data-end="1540">
<p data-start="1470" data-end="1540">Apply and support <strong data-start="1488" data-end="1529">IEEE 1149.1, IEEE 1500, and IEEE 1687</strong> standards.</p>
</li>
<li data-start="1541" data-end="1644">
<p data-start="1543" data-end="1644">Execute and verify <strong data-start="1562" data-end="1581">ATPG (SAF, TDF)</strong> and <strong data-start="1586" data-end="1595">MBIST</strong> using unit-delay and min/max timing simulations.</p>
</li>
<li data-start="1645" data-end="1718">
<p data-start="1647" data-end="1718">Perform detailed <strong data-start="1664" data-end="1690">ATPG coverage analysis</strong> and drive coverage closure.</p>
</li>
<li data-start="1719" data-end="1824">
<p data-start="1721" data-end="1824">Collaborate with <strong data-start="1738" data-end="1776">product and test engineering teams</strong> to deliver manufacturing test patterns for ATE.</p>
</li>
<li data-start="1825" data-end="1911">
<p data-start="1827" data-end="1911">Develop <strong data-start="1835" data-end="1865">diagnostic tools and flows</strong> for ATPG, MBIST, and silicon bring-up on ATE.</p>
</li>
<li data-start="1912" data-end="2040">
<p data-start="1914" data-end="2040">Work hands-on with <strong data-start="1933" data-end="1964">industry-standard DFT tools</strong>, contributing from low-level implementation through architectural planning.</p>
</li>
</ul>
<hr data-start="2042" data-end="2045">
<h2 data-start="2047" data-end="2072">Minimum Qualifications</h2>
<ul data-start="2074" data-end="2571">
<li data-start="2074" data-end="2188">
<p data-start="2076" data-end="2188"><strong data-start="2076" data-end="2101">BE/ME (or equivalent)</strong> in Electrical Engineering, Computer Engineering, Computer Science, or a related field.</p>
</li>
<li data-start="2189" data-end="2260">
<p data-start="2191" data-end="2260"><strong data-start="2191" data-end="2217">7+ years of experience</strong> in DFT, including <strong data-start="2236" data-end="2259">scan test and MBIST</strong>.</p>
</li>
<li data-start="2261" data-end="2329">
<p data-start="2263" data-end="2329">Proficiency with <strong data-start="2280" data-end="2288">HDLs</strong> such as Verilog, SystemVerilog, or VHDL.</p>
</li>
<li data-start="2330" data-end="2416">
<p data-start="2332" data-end="2416">Experience with <strong data-start="2348" data-end="2386">scripting or programming languages</strong> (e.g., Python, Perl, TCL, C).</p>
</li>
<li data-start="2417" data-end="2503">
<p data-start="2419" data-end="2503">Strong ability to collaborate effectively in <strong data-start="2464" data-end="2502">cross-functional and diverse teams</strong>.</p>
</li>
<li data-start="2504" data-end="2571">
<p data-start="2506" data-end="2571">Experience producing <strong data-start="2527" data-end="2570">clear, detailed technical documentation</strong>.</p>
</li>
</ul>
<p> </p>
