Optimize memory system performance (hard real time and soft real time) on critical use cases in pre-silicon phase. Create, improve and maintain the real use cases test vectors.
Develop CPU performance and power modeling on real use cases, to support and suggest architecture decisions.
Collaborate with Architect, Verification, Platform/IP design and Software teams to execute performance closure tests. Analyze performance bottleneck and propose optimization solution in pre-silicon phase.
Host the silicon performance correlation.
Minimum qualifications:
Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, a related field, or equivalent practical experience.
8 years of experience in memory system performance (hard real time and soft real time) in pre-silicon phase.
Experience with performance analysis, including software-hardware interaction and bottleneck identification (CPU, GPU, memory bound).
Experience with memory system components like memory management units, bus fabric, coherent fabric, system level cache and memory controller architecture design and sizing.
Preferred qualifications:
Master's degree or PhD in Electrical Engineering, Computer Engineering or Computer Science, with an emphasis on computer architecture.
Experience with memory system power modeling.
Experience with memory system hard real time analysis and debug.
Experience in power and performance analysis of CPUs, GPUs, TPUs, interconnect fabrics, or memory systems.
Knowledge in one or more of these areas: QoS tuning, bandwidth and latency analysis.
