Develop and support various electronic design automation (EDA) tool infrastructure and flows.
Collaborate with cross-functional teams to debug failures (e.g., boards, software, manufacturing, design, thermal issues, etc.) in lab and simulation.
Work with internal cross-functional teams, including software engineering teams, external silicon partners, and intellectual property (IP) vendors to functionally validate and parametrically characterize the silicon and correlate that results meet predicted values.
Influence Tensor Mobile SoC power architecture decisions for optimal Power Purchase Agreement (PPA) working cross-functionally with product, architects, software, and implementation teams.
Lead proposed solutions through the entire development life-cycle, guiding their evolution from concept to a Hardware/Software optimized system solution deployed within the SoC and through production Software.
Minimum qualifications:
Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, a related field, or equivalent practical experience.
8 years of experience with ASIC power management architecture.
8 years of experience with hardware or software power control flows and methodology.
Preferred qualifications:
Master's degree or PhD in Electrical Engineering, Computer Engineering or Computer Science, with an emphasis on computer architecture.
6 years of experience with power components, power modeling, and power management techniques such as Dynamic Voltage Frequency Scaling (DVFS)/Adaptive Voltage Scaling (AVS), etc.
Experience with processor core architectures (such as ARM, x86, RISC-V, etc.) and IPs commonly used in SoC designs.
