Own micro-architecture and implementation of complex subsystems.
Work with Architecture, Firmware and Software teams to drive feature closure and develop microarchitecture specifications.
Drive design methodology, libraries, debug, code review in coordination with other IPs Design Verification (DV) teams and physical design teams.
Identify and drive Power, Performance and Area improvements for the domains owned.
Minimum qualifications:
Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience.
8 years of experience in Application-Specific Integrated Circuit/System on a chip (ASIC/SoC) development with Verilog/SystemVerilog.
Experience in micro-architecture and design of IPs and Subsystems.
Experience in ASIC design verification, synthesis, timing/power analysis, and Design for Testing (DFT).
Preferred qualifications:
Master's or PhD degree in Electrical Engineering, Computer Engineering, or Computer Science, with an emphasis on computer architecture.
Experience with scripting languages (e.g., Python or Perl).
Experience in SoC designs and integration flows.
Knowledge of high performance and low power design techniques.
Knowledge of bus architectures, fabrics/NoC, processor design, accelerators, or memory hierarchies.
