Define and drive to the implementation of physical design Static Timing Analysis (STA) methodologies.
Take ownership of STA of one or more physical design partitions and top level.
Drive to the closure of timing and power consumption of the design.
Contribute to design methodology, libraries, and code review.
Define the physical design STA constraints rule sets for the Physical design engineers.
Minimum qualifications:
Bachelor’s degree in Electrical Engineering or equivalent practical experience.
5 years of experience with advanced design, including clock/voltage domain crossing, Design for Testing (DFT), and low power designs.
5 years of experience with Static Timing Analysis (STA) convergence on blocks, Subsystem (SS) or SoC.
Experience with System on a Chip (SoC) cycles.
Experience in high-performance, high-frequency, and low-power designs.
Preferred qualifications:
Master’s degree in Electrical Engineering.
Experience in coding with System Verilog and scripting with Tool Command Language (TCL).
Experience in VLSI design in SoC or experience with multiple-cycles of SoC in ASIC design.
Experience in coding constraints and scripting with TCL.
