Architecture & Micro-Architecture
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Define product feature and capabilities and own the architecture for compute, memory, interconnect & high-speed interface subsystems in the AI inference chip.
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Collaborate with various software teams to co-optimize hardware features for AI workloads.
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Collaborate with RTL designers to identify complex technical issues/risks. Review and guide RTL implementation, ensuring consistency with architectural intent and timing/power goals
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Collaborate with Physical-design teams for Area/Floorplan refinement, Timing targets etc.
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Define and document interface specifications, control/status logic, and pipeline structures.
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Lead PPA analysis and trade-off discussions across RTL and architecture.
AI Workloads & HW-SW Co-Design
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Collaborate closely with various software to co-optimize hardware features for real-world AI inference workloads.
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Incorporate considerations such as, quantization, sparsity, dataflow, scheduling, memory bandwidth into architectural decisions.
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Guide hardware features that improve programmability, debuggability, and long-term software scalability.
Modelling & Analysis
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Develop and maintain high-level architecture and performance models.
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Use simulation and architectural models to guide RTL-level improvements.
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Validate model predictions against RTL or emulation results and refine accordingly.
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Strong understanding of AI inference workloads, dataflows, quantization, and memory/bandwidth bottlenecks in edge deployments
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