Develop DFT strategy and architecture (e.g., hierarchical DFT, DFT for High speed IOs, Analog DFT).
Develop and drive die level DFT validation strategy and complete all Test Design Rule Checks (TDRC) and design changes to fix TDRC violations to achieve high-test quality.
Integrate DFT logic, boundary scan, scan chains, DFT compression, Logic BIST, TAP controller, clock control block, and other DFT IP blocks.
Document DFT architecture, test sequences, and boot-up sequences associated with test pins.
Generate and deliver the production and debug patterns to Post Silicon Engineering team and run diagnosis for post silicon supports.
Minimum qualifications:
Bachelor's degree in Electrical, Electronics, Communication, Computer Engineering, a related field, or equivalent practical experience.
8 years of experience with implementation and validation of various DFT technologies.
Experience with multiple projects in DFT design and verification, DFT specification, definition, architecture, and insertion.
Experience with DFT techniques and tools, ASIC DFT synthesis, simulation, and verification flow.
Experience in leading DFT activities throughout an ASIC development flow.
Preferred qualifications:
Master's degree in Electrical Engineering, or a related field.
Experience in IP integration (e.g., memories, test controllers, TAP, and MBIST).
Experience in SoC cycles, including silicon bring-up and silicon debug activities.
Experience in fault modeling.
