Define block-level design documents (e.g., interface protocols, block diagrams, transaction flows, pipelines, etc.).
Perform RTL coding, function or performance simulation debugging, and Lint, Clock Domain Crossing (CDC), Formal Verification (FV), and Unified Power Format (UPF) checks.
Participate in synthesis, timing and power closure, and FPGA or silicon bring-up.
Work on sub-system and chip-level integration activities, including: task planning, holding code and design reviews, and developing features.
Interact with the architecture team to develop implementation (microarchitecture and coding) strategies to meet quality, schedule, and PPA targets for sub-system and chip-level integration.
Minimum qualifications:
Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience.
8 years of experience with digital logic design principles, RTL design concepts, and languages (e.g., Verilog or SystemVerilog).
8 years of experience with logic synthesis techniques to optimize RTL code, performance, and power, as well as low-power design techniques.
Experience with high-performance design and multi-power domains with clocking.
Preferred qualifications:
Master's or PhD degree in Electrical Engineering, Computer Engineering, or Computer Science.
Experience with ASIC or FPGA design verification, synthesis, timing/power analysis, and DFT.
Experience with ASIC design methodologies for front quality checks (e.g., Lint, CDC/RDC).
Experience in high-performance design, multi-power domains with clocking, and multiple SoCs with silicon success.
Knowledge of memory compression, fabric, coherence, cache, or DRAM.
