Drive design methodology, libraries, debug, code review in co-ordination with other IP Design Verification (DV) teams and Physical Design teams.
Identify and drive power, performance and area of improvements.
Participate in design, implementation and integration of chassis and subsystems.
Perform RTL coding for Subsystems/SoC integration, function/performance simulation debug, Lint/CDC/FV/UPF checks.
Perform quality check flows like Lint, CDC, RDC, VCLP.
Minimum qualifications:
Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience.
4 years of experience in ASIC development with Verilog/SystemVerilog, Very High Speed Integrated Circuit (VHSIC), Hardware Description Language (VHDL), or Chisel.
Experience with micro-architecture and designing IPs and subsystems.
Experience in one coding/scripting language (e.g., Python, Perl).
Preferred qualifications:
Master's or PhD degree in Electrical Engineering, Computer Engineering, or Computer Science.
Experience in System on a Chip (SoC) designs and integration flows.
Experience in AI/ML.
Knowledge of arithmetic units, bus architectures, processor design, accelerators, or memory hierarchies.
Knowledge of high performance and low power design techniques.
