Participate in synthesis, timing/power closure, and Field Programmable Gate Array (FPGA)/silicon bring-up.
Participate in test plan and coverage analysis of the block and ASIC-level verification.
Modify ASIC Register-Transfer Level (RTL) for a given IP/subsytem to a dedicated FPGA prototyping platform.
Run the end-to-end FPGA flow (including synthesis, place and route, timing) for an IP/subsystem.
Develop the necessary collaterals (tests, porting scripts) to bring-up the IP/subsystem on the FPGA platform.
Minimum qualifications:
Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience.
4 years of experience with digital logic design principles, RTL design concepts, and languages, such as Verilog or SystemVerilog.
3 years of experience in ASIC design flows and methodologies, IP integration (subsystems, memories, IO's and analog IP) and RTL design.
Experience with logic synthesis techniques to optimize RTL code, performance and power, as well as low-power design techniques.
Experience in the semiconductor industry, with experience in emulation or FPGA prototyping.
Preferred qualifications:
Master's or PhD degree in Electrical Engineering, Computer Engineering, or Computer Science.
Experience in a scripting language like Perl or Python.
Knowledge of high-performance and low-power design techniques, assertion-based formal verification, FPGA and emulation platforms, and SOC architecture.
