Own microarchitecture and implementation of Internet Protocol (IP) and subsystems.
Work with Architecture, Firmware, and Software teams to drive feature closure and develop micro-architecture specifications.
Drive design methodology, libraries, debug, code review in coordination with other IP Design Verification (DV) teams and physical design teams.
Identify and drive power, performance and area of improvements.
Minimum qualifications:
Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, a related field, or equivalent practical experience.
4 years of experience in ASIC development with Verilog, SystemVerilog, Very High Speed Integrated Circuit (VHSIC), Hardware Description Language (VHDL), or Chisel.
Experience with micro-architecture and designing IPs and subsystems.
Experience in ASIC design verification, synthesis, timing/power analysis, and design for testing (DFT).
Preferred qualifications:
Experience with coding languages (e.g., Python or Perl).
Experience in System on a Chip (SoC) designs and integration flows.
Knowledge of arithmetic units, bus architectures, processor design, accelerators, or memory hierarchies.
Knowledge of high performance and low power design techniques.
