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<div><strong>Job Title: Principal Physical Design Engineer (RTL-to-GDSII)</strong></div>
<div><strong>Experience:</strong> 14+ Years</div>
<div><strong>Technology Focus:</strong> Sub-5nm (3nm/2nm)</div>
<div><strong>Location:</strong> Bangalore Hybrid</div>
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<div><strong>The Vision</strong></div>
<div>We are seeking a<span class="Apple-converted-space"> </span><strong>Principal Physical Design Engineer</strong> who thrives on complexity and rejects the "black box" approach to EDA tools. This role is for a<span class="Apple-converted-space"> </span><strong>First Principles thinker</strong> who questions the status quo. If a standard flow isn't yielding the desired PPA (Power, Performance, Area), you dive into the PDK, the tool algorithms, and the methodology to find a better way. You are responsible for transforming raw RTL into world-class silicon by eliminating systemic bottlenecks and building a scalable, predictable path to GDSII.</div>
<div><br><strong>Key Responsibilities</strong></div>
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<li><strong>Full-Flow Ownership:</strong> Lead the implementation of massive, high-speed blocks/SoCs from Synthesis through Sign-off using the<span class="Apple-converted-space"> </span><strong>Cadence Digital Suite</strong>.</li>
<li><strong>PPA Optimization:</strong> Push the theoretical limits of the PDK and tools. You will analyze and optimize the interplay between library cells, metal stacks, and tool engines to squeeze out every millivolt and picosecond.</li>
<li><strong>Methodology & Scalability:</strong> Build and refine a "Push-Button" style execution methodology that is robust, repeatable, and minimizes manual "human-in-the-loop" iterations.</li>
<li><strong>Cross-Functional "Left-Shift":</strong> Collaborate with RTL, Architecture, and DFT teams to influence design decisions early. You will drive a holistic approach where physical constraints inform the architecture, not just react to it.</li>
<li><strong>Bottleneck Elimination:</strong> Identify "drag" in the execution pipeline—whether it’s runtime, convergence issues, or tool limitations—and architect automated solutions to bypass them.</li>
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<div><strong>Technical Qualifications</strong></div>
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<div><strong>Experience</strong></div>
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<div>14+ years in Physical Design with a proven track record of multiple<span class="Apple-converted-space"> </span><strong>sub-5nm</strong> tape-outs.</div>
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<div><strong>Tool Suite</strong></div>
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<div>Mastery of<span class="Apple-converted-space"> </span><strong>Cadence Innovus</strong>, Tempus, Joules, Pegasus, and Voltus.</div>
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<div><strong>Advanced Nodes</strong></div>
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<div>Deep understanding of sub-5nm physics: EUV constraints, multi-patterning, FinFET and IR/EM challenges.</div>
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<div><strong>Sign-off</strong></div>
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<div class="elementToProof">Expert-level knowledge in Static Timing Analysis (STA), Physical Verification (PV), and Power Integrity (PI) and ECO methodology.</div>
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<div><strong>Scripting</strong></div>
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<div>Proficiency in<span class="Apple-converted-space"> </span><strong>Tcl and Python</strong> to develop custom flow wrappers and data-mining tools for PPA analysis.</div>
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<div><strong>Soft Skills & Leadership</strong></div>
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<li><strong>Holistic Thinking:</strong> You look at the "Big Picture." You solve timing by fixing the floorplan or the RTL/ARCH</li>
<li><strong>Influence & Rapport:</strong> You can build strong technical bridges with Front-End, Foundry, and EDA vendors to align on a unified execution strategy.</li>
<li><strong>Critical Thinking:</strong> You operate on first principles. You don't just follow a vendor's "Best Practices" if they don't make sense for our specific architecture.</li>
<li><strong>Mentorship:</strong> You act as a force multiplier, elevating the technical competence of the entire PD team.</li>
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<div><strong>Why Join This Team?</strong></div>
<div>In this role, you aren't just a "user" of tools; you are an engineer who shapes how silicon is built. You will have the autonomy to overhaul legacy flows and the resources to execute on cutting-edge nodes that define the industry's future.</div>
