Providing technical leadership and expertise to define requirements for framework through programming/scripting of verification and emulation flows.
Partnering with ASIC engineers to deploy and support framework for technologies like advanced verification environment configuration and management.
Collaborating cross-functionally to optimize verification and emulation workflows and standardize methodologies.
BE or MS degree in Electrical Engineering or Computer Engineering, with 8+ years of experience.
Understanding C, SystemVerilog UVM, coverage driven verification methodology especially testplan creation and constructs of testbench architecture.
Scripting and regression suite development experience using Python, TCL and Perl
Excellent debugging and problem-solving skills with simulation and emulation environments.
Skills Required:
Proficiency with SystemVerilog UVM and advanced verification methodologies.
Good Programming/Scripting skills with languages such as Python, Perl, TCL and BASH
Working knowledge of Linux/Unix environment and shell scripting
Excellent debugging and problem-solving skills with simulation and emulation environments. Experience with test plan creation and execution.
Cross-Functional Collaboration: Ability to work closely with design, validation, firmware, and physical design teams to resolve system-level issues.
Strong team player, able to collaborate effectively across architecture, design, and validation teams.
Great written and verbal communication skills
Strong team player who can collaborate with colleagues
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