Play senior verification member role and development of verification of SoC level scenarios and IP integration verification
Owning the Testbench architecture and development
Thriving to bring innovation in Verification Methodologies and optimizing the flow and turn around time.
Key contributor for post silicon validation support, pattern generation.
Develop tests , Debug failures and perform root cause analysis
Develop/execute/debug test cases in simulation and Pre-Sillicon Validation on palladium
Collaborate with validation and FW teams.
Working closely with different teams within organization and tracking bugs to closure
Be involved in SOC bring-up and Pre/Post Si Validation
B.E/B.Tech with 8 years of experience in SoC verification/post silicon debug
Excellent design and verification concepts
Experience in C based SoC verification and methodologies
Experience in PCIe transport and link layers and/or NVME architecture
The ideal individual must have proven ability to achieve results in a fast moving, dynamic environment.
Self-motivated and self-directed, however, must have demonstrated ability to work well with people
A proven desire to work as a team member, both on the same team and outside of the team.
Ability to troubleshoot and analyze complex problems. Ability to multi-task and meet deadline
Excellent communication (written and verbal) and interpersonal skills
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ion will be kept confidential according to EEO guidelines.
