At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology.
Cadence IP Tensilica group is a leading provider of configurable embedded processor technology, with a growing presence in the Automotive Safety market. As a member of the Functional Safety Design Verification Team for Xtensa processors you will be responsible for development and verification of hardware and software safety mechanisms. You will implement simulation or emulation test benches, assembly/C language diagnostics, assertion checkers or coverage monitors to meet target safety and product verification goals. You will also assist with fault simulation and analyzing coverage information. You will work closely with the RTL, EDA, and Functional Safety teams. You will develop and deliver functional safety work products, including documentation needed for product safety certification.
Required Skills and Experience
:
8-10 years of design verification experience
BS (or higher) in EE/Computer Engineering
Experience in leading a small team
Excellent knowledge of computer architecture/micro-architecture and design verification fundamentals
Expertise with Verilog and popular EDA simulation, SystemVerilog assertions and functional coverage
Good working knowledge of scripting languages like Perl, Unix shell or similar languages
Knowledge of technical safety concepts and requirement specifications according to ISO 26262
Proficient with C language and assembly language
Excellent written and oral communication skills necessary
Exposure to debugging netlist/gate level simulation.
General understanding OS.
Exposure to MISRA coding guidelines
Experience in fault simulation tools and methodologies
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