<p>EnCharge AI is a leader in advanced AI hardware and software systems for edge-to-cloud computing. EnCharge’s robust and scalable next-generation in-memory computing technology provides orders-of-magnitude higher compute efficiency and density compared to today’s best-in-class solutions. The high-performance architecture is coupled with seamless software integration and will enable the immense potential of AI to be accessible in power, energy, and space constrained applications. EnCharge AI launched in 2022 and is led by veteran technologists with backgrounds in semiconductor design and AI systems.</p>
<div class="elementToProof"><strong>Physical Design Engineer (2-4 Years Experience)</strong></div>
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<div class="elementToProof">We are looking for a high-caliber<span class="Apple-converted-space"> </span><strong>Physical Design Engineer</strong> to join our fast-paced startup team. This role is designed for "top 1%" talent—engineers from<span class="Apple-converted-space"> </span><strong>tier-1 universities (IIT/NIT/BITS or equivalent)</strong> who possess a relentless "go-getter" attitude and the critical thinking skills required to solve complex, next-generation silicon challenges.</div>
<div class="elementToProof">If you are eager to move beyond standard digital flows into the future of<span class="Apple-converted-space"> </span><strong>AI-driven automation</strong>, this is your playground.</div>
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<div class="elementToProof"><strong>Key Responsibilities</strong></div>
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<div class="elementToProof"><strong>End-to-End Ownership:</strong> Drive RTL-to-GDSII implementation, including floorplanning, placement, CTS, routing, and physical verification (LVS/DRC/ERC).</div>
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<div class="elementToProof"><strong>Performance Optimization:</strong> Execute high-performance design closure focusing on<span class="Apple-converted-space"> </span><strong>PPA (Power, Performance, Area)</strong> targets in advanced process nodes ( 3nm or below)</div>
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<div class="elementToProof"><strong>Static Timing Analysis (STA):</strong> Perform comprehensive timing closure, including signal integrity, crosstalk analysis, and<span class="Apple-converted-space"> </span><strong>CPPR (Common Path Pessimism Removal)</strong> optimization.</div>
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<div class="elementToProof"><strong>Power Integrity:</strong> Conduct IR-drop analysis (Static/Dynamic) and EM (Electromigration) checks to ensure robust power delivery.</div>
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<div class="elementToProof"><strong>Innovation:</strong> Develop and integrate<span class="Apple-converted-space"> </span><strong>AI/ML-based automation scripts</strong> to optimize the physical design flow and reduce turnaround time.</div>
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<div class="elementToProof"><strong>Qualifications & Requirements</strong></div>
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<div class="elementToProof"><strong>Education:</strong> B.Tech/M.Tech<span class="Apple-converted-space"> </span>in Electrical/Electronics Engineering from a<span class="Apple-converted-space"> </span><strong>Top Tier University</strong>.</div>
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<div class="elementToProof"><strong>Experience:</strong> 2–4 years of hands-on experience in Physical Design within the semiconductor industry.</div>
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<div class="elementToProof"><strong>Tool Expertise:</strong> Expert-level proficiency in industry-standard tools (Preferred<span class="Apple-converted-space"> </span><strong>Innovus</strong>).</div>
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<div class="elementToProof"><strong>Technical Depth:</strong> Strong understanding of multi-corner multi-mode (MCMM) closure, low-power design techniques (UPF/CPF), and physical verification.</div>
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<div class="elementToProof"><strong>Mindset:</strong> A proven "go-getter" who is diligent, detail-oriented, and capable of taking complete ownership of blocks under tight deadlines.</div>
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<div class="elementToProof"><strong>The "Plus":</strong> Proficiency in Python/Tcl and experience using<span class="Apple-converted-space"> </span><strong>AI/ML models for EDA tool automation</strong> or predictive PPA analysis.</div>
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<div class="elementToProof">Location: Bangalore</div>
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