Develop all aspects of ASIC RTL2GDS implementation for high Performance, Power, Area (PPA) designs.
Manage block level physical implementation and QoR (power, timing, area).
Minimum qualifications:
Bachelor's degree in Mechanical Engineering, Electrical Engineering, Industrial Engineering, or equivalent practical experience.
8 years of experience with physical design.
Experience with sign-off optimizations, sign-off convergence, including Static Timing Analysis (STA), electrical checks, and physical verification.
Experience with one or more of synthesis/PnR tools (e.g., Genus, Innovus, DC and ICC, STA tools).
Experience working with chip tape outs.
Preferred qualifications:
Experience with high-performance designs (e.g., CPUs, GPUs, etc.).
Experience with 7nm, 5nm, 3nm, or 2nm nodes.
