Use analytical and simulation techniques to ensure performance, power, and area (PPA) is within defined requirements.
Collaborate with cross-functional teams to debug failures or performance shortfalls program goals in lab or simulation.
Design chips, chip-subsystems, or partitions within subsystems from synthesis through place, route and sign off convergence, ensure that the design meets the architecture goals of power, performance, and area.
Develop, validate, and improve electronic design automation (EDA) methodology for a specialized sign off or implementation domain to enable cross-functional teams to build and deliver blocks that are correct by construction and ease convergence efforts.
Minimum qualifications:
Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience.
4 years of experience with physical design (e.g., from RTL to GDSII, including key stages like synthesis, floorplanning, place and route, and timing closure).
Preferred qualifications:
Master's degree or PhD in Electrical Engineering, Computer Engineering or Computer Science, with an emphasis on computer architecture.
Experience with scripting languages such as Perl, Python, or Tcl.
Experience with constraints, synthesis or clock tree synthesis (CTS)
