Microarchitect and RTL Design Engineer

<div class="content-intro"><p><strong>Baya Systems is inspired by the&nbsp;<a href="https://bayasystems.com/about/">baya bird</a>, also known as the&nbsp;<a href="https://bayasystems.com/about/">weaver</a>. Baya birds weave very unique and intricate hanging nests from different materials. The nests are robust and safe while being extremely lightweight and efficient.</strong></p> <p>Baya is a fast-moving Series B startup built by serial entrepreneurs with a vision to accelerate intelligent computing in the emerging chiplet era. &nbsp;We focus on software-driven, unified fabric solutions for single-die and multi-die systems. We design and license disruptive intellectual property for use in semiconductor chips, with software development platforms to simplify the design process and reduce the time to market for complex System-on-Chip (SoC) and multi-chiplet systems. This enables our partners to innovate and deliver compelling solutions for data center, infrastructure, AI, Automotive, and Edge IoT markets. We are looking for energetic and dedicated individuals share our passion for enabling innovation and excellence in the semiconductor industry that empowers game-changing products and services!</p></div><p>MICROARCHITECT AND RTL DESIGN&nbsp;&nbsp;</p> <p class="font_8 wixui-rich-text__text">BENGALURU, INDIA</p> <p class="font_8 wixui-rich-text__text"><span class="wixui-rich-text__text">About the role:</span></p> <p class="font_8 wixui-rich-text__text"><span class="wixui-rich-text__text">We are seeking a seasoned Microarchitect and RTL Design Engineer with a strong background in microarchitecture and RTL coding. The ideal candidate will play a key role in shaping our technology portfolio, bringing expertise and creativity to our solutions</span></p> <p class="font_8 wixui-rich-text__text"><span class="wixui-rich-text__text">Responsibilities:</span></p> <ul class="font_8 wixui-rich-text__text"> <li class="wixui-rich-text__text"> <p class="font_8 wixui-rich-text__text"><span class="wixui-rich-text__text">Design and develop microarchitectures for a set of highly configurable IP's</span></p> </li> <li class="wixui-rich-text__text"> <p class="font_8 wixui-rich-text__text"><span class="wixui-rich-text__text">Microarchitecture and RTL coding ensuring optimal performance, power, area</span></p> </li> <li class="wixui-rich-text__text"> <p class="font_8 wixui-rich-text__text"><span class="wixui-rich-text__text">Collaborate with software teams to define configuration requirements, verification collaterals etc.</span></p> </li> <li class="wixui-rich-text__text"> <p class="font_8 wixui-rich-text__text"><span class="wixui-rich-text__text">Work with verification teams on assertions, test plans, debug, coverage etc.</span></p> </li> </ul> <p class="font_8 wixui-rich-text__text"><span class="wixui-rich-text__text">Qualifications and Preferred Skills:</span></p> <ul class="font_8 wixui-rich-text__text"> <li class="wixui-rich-text__text"> <p class="font_8 wixui-rich-text__text"><span class="wixui-rich-text__text">BS, MS in Electrical Engineering, Computer Engineering or Computer&nbsp;</span><span class="wixui-rich-text__text">Science</span></p> </li> <li class="wixui-rich-text__text"> <p class="font_8 wixui-rich-text__text">8+ years and current hands-on experience in microarchitecture and RTL development</p> </li> <li class="wixui-rich-text__text"> <p class="font_8 wixui-rich-text__text">Proficiency in Verilog, System Verilog</p> </li> <li class="wixui-rich-text__text"> <p class="font_8 wixui-rich-text__text">Familiarity with industry-standard EDA tools and methodologies</p> </li> <li class="wixui-rich-text__text"> <p class="font_8 wixui-rich-text__text">Experience with large high-speed, pipelined, stateful designs, and low power designs</p> </li> <li class="wixui-rich-text__text"> <p class="font_8 wixui-rich-text__text">In-depth understanding of on-chip interconnects and NoC's</p> </li> <li class="wixui-rich-text__text"> <p class="font_8 wixui-rich-text__text">Experience within Arm ACE/CHI or similar coherency protocols</p> </li> <li class="wixui-rich-text__text"> <p class="font_8 wixui-rich-text__text">Experience designing IP blocks for caches, cache coherency, memory subsystems, interconnects and NoC's</p> </li> <li class="wixui-rich-text__text"> <p class="font_8 wixui-rich-text__text">Familiarity with RAS designs, QoS in fabrics, PCIe/IO is a plus</p> </li> <li class="wixui-rich-text__text"> <p class="font_8 wixui-rich-text__text"><span class="wixui-rich-text__text">Experience with modern programming languages like Python is a plus</span></p> </li> <li class="wixui-rich-text__text"> <p class="font_8 wixui-rich-text__text">Excellent problem-solving skills and attention to detail</p> </li> <li class="wixui-rich-text__text"> <p class="font_8 wixui-rich-text__text">Strong communication and collaboration skills</p> </li> </ul> <p>&nbsp;</p><div class="content-conclusion"><p><strong>Compensation:</strong></p> <ul> <li>Salary commensurate with experience</li> <li>Performance incentives</li> <li>Comprehensive medical, dental, and vision benefits</li> <li>401(k) retirement plan</li> <li>Equity</li> </ul> <p>&nbsp;</p></div>