Set technical direction for the team within the capacity of technical lead and people manager.
Engage with Machine Learning System Architects and Software teams to define specifications and implement digital logic using Chisel, Verilog, and/or SystemVerilog.
Engage with Verification and Silicon Validation teams to ensure functionality of the design.
Perform power, area, and performance trade-offs of digital designs and architectures.
Apply engineering best practices (e.g., code review, testing, refactoring) to the design and implementation of ASIC blocks.
Minimum qualifications:
Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience.
8 years of experience with digital logic design principles, RTL design concepts, and languages, such as Verilog or SystemVerilog.
Experience with logic synthesis techniques to optimize RTL code, performance and power, as well as low-power design techniques.
Preferred qualifications:
Master's or PhD degree in Electrical Engineering, Computer Engineering or Computer Science.
Experience with a scripting language like Perl or Python.
Experience with ASIC or FPGA design verification, synthesis, timing/power analysis, and DFT.
Knowledge of high-performance and low-power design techniques, assertion-based formal verification, FPGA and emulation platforms, and SOC architecture.
Knowledge of memory compression, fabric, coherence, cache, or DRAM.
