Role Overview
We are seeking a highly motivated DSP Engineer to join our Automotive Ethernet PHY development team. In this role, you will work closely with the DSP Architect to implement and optimize DSP algorithms and architecture for next‑generation automotive-grade Ethernet PHY products. The role requires strong collaboration with System Architecture, DFT, Verification, Validation, IC Integration, and Backend (BE) teams.
You will be responsible for DSP design implementation, RTL-level integration, performance validation, and supporting timing closure to ensure high‑quality, production-ready silicon.
Key Responsibilities
DSP Architecture Implementation
Implement DSP algorithms and architecture under guidance of the DSP Architect for Automotive Ethernet PHY (e.g., 100/1000BASE-T1 and multi‑gig PHYs).
Translate system‑level specifications into optimized DSP RTL design.
Participate in algorithm-to-architecture mapping, fixed‑point modeling, and performance tuning.
Design & RTL Development
Develop synthesizable RTL for DSP datapaths, filters, equalizers, echo cancellation, FFE/DFE, AGC, timing recovery, etc.
Perform design optimization for area, timing, and power.
Create and maintain design documentation, micro‑architecture specs, and implementation notes.
Verification & Validation Support
Work closely with the Verification team for test plan development, debug, and coverage closure.
Support Validation team during post‑silicon bring‑up, debug, and performance tuning.
Contribute to model correlation between MATLAB/C-model and RTL.
Cross‑Functional Collaboration
Collaborate with System Architects to refine requirements and improve DSP behavior at system level.
Work with DFT Architects to ensure testability and seamless integration of DFT structures.
Partner with IC integrators to define top-level constraints and support SoC integration.
Support Backend (BE) teams for timing analysis, timing closure, and physical design iterations.
Performance, Tools & Flow
Develop and maintain MATLAB/Python models for algorithm validation.
Run simulations, analyze performance metrics, and support model-to-RTL equivalence.
Contribute to tool flow improvements across DSP modeling, RTL implementation, and validation.
Required Qualifications
Bachelor’s or Master’s degree in Electrical Engineering, Electronics, Communication Engineering, or related field.
7+ years of experience in DSP design for communication systems.
Strong fundamentals in digital signal processing, communication theory, and PHY layer technologies.
Hands-on experience with PHY subsystems such as filtering, equalization, echo cancellation, PLLs, timing recovery, and noise mitigation.
Proficiency in MATLAB, Simulink, Python, or C/C++ for algorithm modeling.
Strong RTL design skills (Verilog/SystemVerilog).
Familiarity with synthesis, linting, CDC, and STA flows.
Experience supporting verification and post‑silicon debug.
Preferred Qualifications
Experience in Automotive Ethernet PHY (100BASE‑T1, 1000BASE‑T1, or multi‑gig).
Understanding of EMC/EMI challenges and automotive-grade requirements.
Knowledge of DFT, ATPG, and scan architectures.
Exposure to backend flows, timing constraints, and timing closure methodologies.
Familiarity with formal verification and UVM-based environments.
Soft Skills
Strong analytical and problem‑solving skills.
Excellent communication and documentation ability.
Ability to work effectively in cross‑functional, global teams.
Proactive mindset with the ability to drive tasks to closure.
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