<p>EnCharge AI is a leader in advanced AI hardware and software systems for edge-to-cloud computing. EnCharge’s robust and scalable next-generation in-memory computing technology provides orders-of-magnitude higher compute efficiency and density compared to today’s best-in-class solutions. The high-performance architecture is coupled with seamless software integration and will enable the immense potential of AI to be accessible in power, energy, and space constrained applications. EnCharge AI launched in 2022 and is led by veteran technologists with backgrounds in semiconductor design and AI systems.</p>
<p class="ms-outlook-mobile-reference-message skipProofing"><strong>Job Description</strong>: Lead DFT Engineer (Edge Computing)<br>Developing silicon for Edge Computing isn't just about speed; it’s about balancing high-performance data processing with extreme power efficiency and reliability in remote environments.</p>
<p class="ms-outlook-mobile-reference-message skipProofing">As the Design for Test (DFT) Lead, you will be the architect of our testing strategy, ensuring our data center chips are flawlessly manufacturable and resilient enough for edge deployment.</p>
<p class="ms-outlook-mobile-reference-message skipProofing"><strong>Key Responsibilities<br></strong>Architectural Leadership: Define and implement the end-to-end DFT architecture for complex SoCs, including Hierarchical DFT, Scan compression,<span class="Apple-converted-space"> </span><strong><em>Boundary Scan</em></strong> and MBIST.</p>
<p class="ms-outlook-mobile-reference-message skipProofing">Edge-Specific Reliability: Develop strategies for In-System Test (IST) and power-on self-test (POST) to ensure chip health in remote edge data centers.</p>
<p class="ms-outlook-mobile-reference-message skipProofing">Implementation & Flow: Oversee scan insertion, ATPG (Stuck-at, Transition, Path Delay), and<span class="Apple-converted-space"> </span><strong><em>Memory</em></strong>/Logic BIST.</p>
<p class="ms-outlook-mobile-reference-message skipProofing">Cross-Functional Synergy: Collaborate with Design, Physical Design, and Yield teams to ensure high test coverage while minimizing area overhead and power impact<span class="Apple-converted-space"> </span><strong><em>as well as timing analysis</em></strong>.</p>
<p class="ms-outlook-mobile-reference-message skipProofing">Post-Silicon Validation: Lead the bring-up and debug phase on ATE (Automated Test Equipment) to root-cause silicon failures and optimize test time.</p>
<p class="ms-outlook-mobile-reference-message skipProofing"><strong>Technical Requirements</strong><br>Experience: 12+ years in DFT, with at least 2 years in a leadership or principal role.</p>
<p class="ms-outlook-mobile-reference-message skipProofing">Tools: Mastery of industry-standard tools (e.g., Synopsys TestMAX, Siemens/Mentor Tessent, or Cadence Modus).</p>
<p class="ms-outlook-mobile-reference-message skipProofing">Memory & Logic Test: Deep expertise in MBIST (Memory Built-In Self-Test) with repair capabilities,<span class="Apple-converted-space"> </span><strong><em>SCAN</em></strong>,<span class="Apple-converted-space"> </span><strong><em>IJTAG (IEEE 1687)<span class="Apple-converted-space"> </span></em></strong>and boundary scan (IEEE 1149.1/6).</p>
<p class="ms-outlook-mobile-reference-message skipProofing">Advanced Nodes: Proven track record with FinFET nodes (7nm, 5nm, or below).</p>
<p class="ms-outlook-mobile-reference-message skipProofing">Low Power: Experience managing DFT in multi-voltage/power-gated designs—crucial for edge efficiency.</p>
