Manage IP vendors for standard cell libraries, SRAM compilers, GPIO, eFuse, OT, and process sensors.
Analyze architecture and design specifications to drive new circuit designs, including standard cells and memory options, to meet stringent Performance, Power, Area (PPA) and cost goals on process nodes.
Collaborate with foundry and test-chip teams to validate the functionality and characterization of new circuit topologies.
Negotiate design and timelines with 3PIP vendors, engaging in technical and schedule trade-off discussions.
Provide technical support to Architecture, Design, and Physical Design teams to optimize the use of foundation IPs for improved functionality and PPA.
Minimum qualifications:
Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, a related field, or equivalent practical experience.
8 years of experience with advanced foundry process nodes, design-technology co-optimization (DTCO), and circuit-level PPA for standard cells, SRAM, and IO/ESD design.
8 years of experience with CMOS, device physics, and circuit design principles, including the first-party IP, third-party IP, and design service vendor landscape.
8 years of experience with circuit characterization and modeling for digital design flows.
Preferred qualifications:
Master's degree or PhD in Electrical Engineering, Computer Engineering or Computer Science, with an emphasis on computer architecture.
Experience partnering with wafer foundries, specifically in PDK management, design collateral integration, and debugging.
Understanding of physical design implementation and DFT methodologies.
Ability to develop test-chip architectures for advanced circuit characterization and post-silicon validation.
