He is responsible to carry out all assigned tasks with focus on function, quality, test architecture, test coverage, schedule and delivery of verification in time.
Together with other discipline's developers the Verification engineer is defining integration concepts, specifying the IC test requirements, defining related test architecture and verifying implemented functions. The is taking care about process implementation and schedule
IC (ASIC) Verification Engineer is responsible for developing functional models for Analog and/or Digital IPs, Developing Digital and Analog/Mixed signal Test-benches, Interaction between IPs at chip level (analog and digital), Developing test-benches, Functional verification, Technical support of co-workers and IP designers, Provide technical support to test engineers
Collect, discuss and evaluate requirements related to IC test & validation concept(s) in cooperation with other discipline's developers
Actively support system and/or IC concept and architecture definition considering feasibility with semiconductor technologies and test strategy
Apply new validation concepts to the design verification.
Define requirements of the IC validation together in cooperation with other discipline's developers
Specify IC validation characteristics and interfaces within component specification document
Responsible for the technical communication with the ASIC supplier during the whole ASIC development
Judge and approve simulation/design results in consideration of defined system requirements
Decide on optimal IC verification concept based on simulation results and worst-case calculations
Evaluate technical and development risks for IC development together with ASIC PM
Plan time schedule for dedicated ASIC project tasks, track validation progress, perform bench tests
Create and maintain development documents
Apply configuration and change management, apply quality assurance management
From circuits specifications, ASIC verification engineer should specify verification strategies and testbench architectures (SystemVerilog, UVM, C-driven, others) to ensure optimum verification coverages
Elaborate detailed verification plans corresponding to circuit specifications
Develop verification environments and tests/sequences according to verification plans
Responsible of the definition of the verification strategies, of their implementation and of the verification quality
Improve the verification flow
Master of Science in Electrical Engineering/Microelectronics/ VLSI design or similar qualification.
Bachelor of science with advanced course in VLSI Design.
REQUIRED KNOWLEDGE
* Organizational Standard Process and Methods (Risk Management, Project Management..)
* Knowledge of test tools, automation
* System Requirements
* System Architecture
* Functional Safety Management (ISO26262)
* System Security & Privacy Engineering (UNECE WP29)
* Communication
* Knowledge of test process, test methods, techniques and tools
* Capability to analyse and solve problems
* Product knowledge (for his responsiblity
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